All Digital Spread Spectrum Clock Generator For Fast Prototyping
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Abstract
The spread spectrum clock generator produces frequency modulated clock signal with varying period. Spread spectrum clock is used instead of fixed frequency clock signal in digital circuits to reduce the EMI noise generated by clock. Available SSCG designs uses complex modulation control techniques leading to high power consumption. Implementation of complex SSCG design in FPGA during prototype stage will increase the time-to-market of digital systems with SSC. This project presents a full digital spread spectrum clock generator design built by leveraging Digital Phase Locked Loop design. The presented SSCG design is simple and implementation in FPGA is quick due to use of predesigned library modules. A counter based digitally controlled oscillator setup is used to minimize power and complexity. The complete design is implemented using HDL and synthesized. The proposed design shows reduced power consumption compared to existing design
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